1 Chip-level simulation for CDM failures in multi-power ICs
2 Maximum likelihood multipath channel estimation for synchronous-CDM systems
5 Influence of the device package on the results of CDM tests-consequences for tester characterization and test procedure
7 The real CDM field induced ESD waveform from MR heads
8 Influence of tester, test method, and device type on CDM ESD testing
Attenna
9 A correlation study between different types of CDM testers and “real” manufacturing in-line leakage failures
10 Chip-level charged-device modeling and simulation in CMOS integrated circuits
11 Advanced CMOS protection device trigger mechanisms during CDM
12 The importance of standardizing CDM ESD test head parameters to obtain data correlation
13 Issues concerning CDM ESD verification modules-the need to move to alumina
charge plate monitor
14 OCDM a new multicode CDM radio transmission system based on cyclic modified M-sequences-performance evaluation using prototype
15 Performance of multi-carrier CDM and COFDM in fading channels
electrometer
16 Simulation of complete CMOS IO circuit response to CDM stress
17 Advanced CMOS protection device trigger mechanisms during CDM
19 A high-speed DSRC system assisted by an overfill CDM for future seamless road-vehicle communication systems
20 Design and performance of quasi-synchronous multi-carrier CDMA system
22 A route design algorithm for multiple-encoding optical CDM switching network
23 Performance analysis of a multi-code CDM transmission scheme based on cyclic extended spread code as a extension of 3rd generation CDMA system
24 MC-CDM-a promising approach for digital broadcast in the AM-band
25 Degradation of GMR and TMR recording heads using very-short-duration ESD transients
26 Design of integrated services digital broadcasting systems using multirate optical fiber code-division multiplexing
27 Very fast transmission line pulsing of integrated structures and the charged device model
28 Variable-bit-rate video transmission systems using optical fiber code-division multiplexing scheme
35 A simulation analysis of quarter-micron CMOS LSI input circuit behavior under CDM-ESD for protection device improvement
36 Investigation into socketed CDM (SDM) tester parasitics
37 Experiments on high-speed all-optical code-division multiplexing (CDM) systems using a 2n prime code
38 CDM an approach to learning in text categorization
39 Latent gate oxide defects caused by CDM-ESD
40 Quench simulation of the 40 mm aperture SSC-quadrupole magnet connected in series with 50 mm aperture SSC-dipole magnets
41 Database model for design data
42 Error-free 1.24 Gbs 4-chip coherent CDM code converter
46 An experiment on a CDM subcarrier multiplexed optical-fiber local area network
61 Reproducibility of field failures by ESD models - comparison of HBM, socketed CDM and non-socketed CDM
62 A combined socketed and non-socketed CDM test approach for eliminating real-world CDM failures
67 Study of ESD evaluation methods for charged device model
73 ESD evaluation methods for a charged device model
93 ESD failure finger-print-an effective and accurate method for root cause determination
98 Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology
99 Wide-band planar monopole antennas
114 4.5 GHz time domain measurement of voltage transition duration due to micro gap discharge as low voltage ESD
119 A case study on hidden ESD events of GMR HGA dynamic test fixture
120 Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions
123 Latent ESD failures in Schottky barrier diodes
125 ESD-sensitivity study of GMR recording heads with a flex-on-suspension head-gimbal assembly
137 Simulation study for the CDM ESD behaviour of the grounded-gate NMOS
138 A compact model for the grounded-gate nMOS behaviour under CDM ESD stress
139 Charged device model (CDM) metrology limitations and problems
158 Analysis of the charge transfer of models for electrostatic discharge (ESD) and semiconductor devices
162 Analysis of the charge discharge processes for the basic ESD models
192 Constant charge and constant potential models for electrostatic discharge (ESD)
194 A novel on-chip electrostatic discharge (ESD) protection for beyond 500 MHz DRAM
196 Sub-micron chip ESD protection schemes which avoid avalanching junctions
198 Analysis of models for electrostatic discharge (ESD) and semiconductor devices
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